1. Field of the Invention
The invention relates to a method for calculating a timing delay in a repeater network in an electronic circuit according to the preambles of the independent claims.
2. Description of the Related Art
In modern chip design (VLSI) the physical feature size of electrical circuit features, such as wiring, and switching circuit elements is decreasing continuously.
With decreasing feature size opens in the chip's wiring become more and more important as functional yield detractors in chip wiring. Yield losses are directly related to the revenue of semiconductor companies. Nevertheless, the impact of variation increases and endangers parametric yield. The augmentation of Steiner trees as published by Kahng et al. in “Nontree routing for reliability and yield improvement”, IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems, January 2004, p. 148-156, or by Panitz et al. in “Robust Wiring Networks for DfY Considering Timing Constraints”, Proceedings of the Great Lakes Symposium on VLSI, May 2007, p. 43-48, is applied to achieve robustness against opens in unrepeated signal nets. Steiner trees offer a network geometry having the shortest wiring for interconnecting between source and sinks.
It is known that the wire length between repeaters in an optimal buffered line decreases with shrinking technology. It is predicted by Saxena et al. in “Repeater Scaling and its Impact on CAD”, IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems, April 2004, p. 451-463, that 70% of all cells will be repeaters at the 32 nm node.
To overcome this issue, an approach has been proposed in the U.S. patent application Ser. No. 12/166,012 to apply wire and gate redundancy on repeater networks. FIG. 1a depicts an example of such a repeater network. A wiring loop or loop-like structure is applied to connect all sinks (output pins displayed as black squares) of the buffer or repeater network 100. The repeater network 100 is supplied by a source 110. “Sink” and “source” refer always to a “pin”. An output pin refers to a sink or sink pin, whereas an input pin refers to a source pin. Then multiple repeaters 112, 114, 116 are distributed at input pins 120, 122, 124 on the loop to drive the load in the loop caused by interconnects and active circuits attached to the output pins of the loop. The approach is either applied in a cascaded way if the load cannot be driven by a single source or a tree connects the repeater cells to the source. This approach offers robustness against wire and via opens, circuit malfunctions and variation. An important aspect concerning the applicability of the proposed topology is the timing analysis. Static timing analysis models the worst case with respect to a specific timing test in order to guarantee the correct behavior of the circuit.
State-of-the art delay calculation is capable of analyzing wiring loops but there is no known solution to model the worst case in a net with opens and multiple gates with different signal-arrival times at their inputs. Chips that do not operate correctly due to opens can easily be found by static scan testing assuming stuck-at-faults, if the opens are not masked by wiring redundancy. On the other hand, if opens are masked by wiring redundancy, they may cause a parametric fail which is only detectable by delay tests. However, delay tests are too costly to be implemented for most semi-custom applications.
Therefore, static timing analysis (STA) has to model the worst delay in a net with respect to a specific timing test. The setup test checks if a signal arrives in time at the latch input to be stored. This test applies the late mode (LM) assuming the maximum possible delay for each net. In contrast, the hold test checks if the next data does not arrive too early in order to overwrite the data to be stored by a latch. The delays have to be calculated in early mode (EM) assuming the minimum possible delay for a net. As timing verification is computationally extensive the objective is to restrict the number of timing runs.
A known and simplistic solution is to assume an open anywhere in the wiring and calculate the delay looking for the maximum and minimum value. As there are infinite possible open positions that lead to an infinite number of delay calculations this can be approximated by a finite but high number in praxis, e.g. by Monte-Carlo simulation. Furthermore, the number of delay calculations depends on the underlying routing grid that has a fine granularity in most applications.